pyiiasmh

[Arnachy69]

Hello ,

Has Anyone Qt SDK Nokia that works with python 2.2.6 in combination
with pyiiasmh

Greatfull THX

Regards
Arnachy69

[dlevere]

Ask hawkeye2777, I don't have his email address but you can reach him here:

Twitter:
https://twitter.com/hawkeye2777

[Arnachy69]

Thx Great man Dlevere for answering and quick replying
maybe you can help me to
the basic about asm code hacking
for me works the best results when i see instruction videos what to do

thx in advance man
greatfull thx

Regards Arnachy69

[dlevere]

========================
ASM OPCODES
========================

WHAT ARE ASM OPCODES?
Short for "Operation Code," the OpCode identifies the type of instruction and provides some information about the instruction length. Say for example you use the command "NOP" (which stands for "No Operation", this stops the address from operating!!), which it's 16 bit hex value is '0000', you would change the end of your code to whatever you're OpCode's hex value is:

Ex: The address that you found is 81002222 and you want it to not operate. Easy. All you have to do is find the hex value to that OpCode - which NOP's hex value is '9090' (but '0000' works just as well). So you would make the code "81002222 9090" or "81002222 0000."

That's the bare bones of it, but I suggest you learn all the ASM OpCodes and their Hexidecimal worth and if they're 16, 32, or 64 bit (etc). It's pretty cool if you actually learn all the OpCodes hex values, this way you can do pretty much ANYTHING with your codes.

Note that ASM OpCodes are only useful AFTER you find your BP address.

TIP: You can find out more about OpCodes by getting an ASM assembler/disassembler and viewing a RAM dump with it. The best site to get one would be www.dextrose.com . You can tinker with these:

ADD rd,rs,rt: ADD; rd=rs+rt; trap on overflow\$zero,0018($v0)
ADDI rt,rs,imm: ADD IMMEDIATE; rd=rs+imm; trap on overflow
ADDIU rt,rs,imm: ADD IMMEDIATE UNSIGNED; rd=rs+imm; never trap
ADDU rd,rs,rt: ADD UNSIGNED; rd=rs+rt; never trap\$a0
AND rd,rs,rt: logical AND; rd=(rs AND rt)u \$v1,$t6,0AF5
ANDI rt,rs,imm: logical AND IMMEDIATE; rd=(rs AND imm)\$v1)
BCnF offset: BRANCH ON COPROCESSOR n FALSE 000464B8
BCnFL offset: BRANCH ON COPROCESSOR n FALSE LIKELY058(\$sp)
BCnT offset: BRANCH ON COPROCESSOR n TRUE \$zero,0060($sp) BCnTL offset: BRANCH ON COPROCESSOR n TRUE LIKELY8011
BEQ rs,rt,offset: BRANCH ON EQUAL; branch if rs=rt690(\$v0)
BEQL rs,rt,offset: BRANCH ON EQUAL LIKELY; branch if rs=rt
BGEZ rs,offset: BRANCH ON > OR = TO ZERO; branch if rs>=0 (SIGNED)
BGEZAL rs,offset: BRANCH ON > OR = TO ZERO AND LINK; (return adress in \$ra)
BGEZALL rs,offset: BRANCH ON >= TO ZERO AND LINK LIKELY; (return adr in \$ra)
BGEZL rs,offset: BRANCH ON > OR = TO ZERO LIKELY; branch if rs>=0 (SIGNED)
BGTZ rs,offset: BRANCH ON > THAN ZERO; branch if rs>0 (SIGNED)
BGTZL rs,offset: BRANCH ON > THAN ZERO LIKELY; branch if rs>0 (SIGNED)
BLEZ rs,offset: BRANCH ON < OR = TO ZERO; branch if rs<=0 (SIGNED)
BLEZL rs,offset: BRANCH ON < OR = TO ZERO LIKELY; branch if rs<=0 (SIGNED)
BLTZ rs,offset: BRANCH ON < THAN ZERO; branch if rs<0 (SIGNED)
BLTZAL rs,offset: BRANCH ON < THAN ZERO AND LINK; (return adress in \$ra)
BLTZALL rs,offset: BRANCH ON < THAN ZERO AND LINK LIKELY;(return adr in \$ra)
BLTZALL rs,offset: BRANCH ON < THAN ZERO AND LINK LIKELY;(return adr in \$ra)
BLTZL rs,offset: BRANCH ON < THAN ZERO LIKELY; branch if rs<0 (SIGNED)n \$ra)
BNE rs,rt,offset: BRANCH ON NOT EQUAL; branch if rs<>rtf rs<0 (SIGNED)n \$ra)
BNEL rs,rt,offset: BRANCH ON NOT EQUAL LIKELY; branch if rs<>rtSIGNED)n \$ra)
BREAK : BREAKPOINT; Breakpoint trap occursELY; branch if rs<>rtSIGNED)n \$ra)
CACHE op,offset(base): not yet implemented rt = COPn control reg rdED)n \$ra)
CFCn rt,rd: MOVE CONTROL FROM COPROCESSOR; rt = COPn control reg rdED)n \$ra)
COPn : Coprocessor n OperationCOPROCESSOR; rt = COPn control reg rdED)n \$ra)
CTCn rt,rd: MOVE CONTROL TO COPROCESSOR; COPn control reg rd = rtrdED)n \$ra)
DADD rd,rs,rt: Doubleword ADD; rd=rs+rt; (MUST BE IN 64 BIT MODE)E)ED)n \$ra)
DADDI rt,rs,imm: Doubleword ADD IMMEDIATE; rt=rs+imm; (64 BIT MODE) BIT)\$ra)
DADDIU rt,rs,imm: Doubleword ADD IMMEDIATE UNSIGNED; rt=rs+imm; (64 BIT)\$ra)
DADDU rd,rs,rt: Doubleword ADD UNSIGNED; rd=rs+rt; (64 BIT MODE)(64 BIT)\$ra)
DDIV rs,rt: Doubleword DIVIDE; LO=rs/rt; HI=rs mod rt; (B4 BIT MODE) BIT)ra)
DDIVU rs,rt: Doubleword DIVIDE UNDIGNED; LO=rs/rt; HI=rs mod rt; (B4 BIT)ra)
DIV rs,rt: DIVIDE; LO=rs/rt; HI=rs mod rt; no trap HI=rs mod rt; (B4 BIT)ra)
DIVU rs,rt: DIVIDE UNSIGNED; LO=rs/rt; HI=rs mod rt; no trap4 BIT MODE)T)ra)
DMFCn rt,rd: Doubleword MOVE FROM SYS CONTROL COPROCESSOR (64 BIT MODE)))ra)
DMULT rs,rt: Doubleword MULTIPLY; LO=low(rs*rt) HI=high(rs*rt); (64 BIT))ra)
DMULTU rs,rt: Doubleword MULTIPLY UNSIGNED; (MUST BE IN 64 BIT MODE)IT))ra)
DSLL rd,rt,sa: Doubleword SHIFT LEFT LOGICAL; rd=rt<<sa (64 BIT MODE) BIT)a)
DSLLV rd,rt,rs: Doubleword SHIFT LEFT LOGICAL VARIABLE; rd=rt<<rs (64 BIT)a)
DSLL32 rd,rt,sa: Doubleword SHIFT LEFT LOGICAL+32; rd=rt<<(sa+32) (64 BIT)a)
DSRA rd,rt,sa: Doubleword SHIFT RIGHT ARITHMETIC; rd=rt>>sa (64 BIT MODE))a)
DSRAV rd,rt,rs: Doubleword SHIFT RIGHT ARITHMETIC VARIABLE; (64 BIT MODE))a)
DSRA32 rd,rt,sa: Doubleword SHIFT RIGHT ARITHM+32; rd=rt>>(sa+32) (64 BIT)a)
DSRL rd,rt,sa: Doubleword SHIFT RIGHT LOGICAL; rd=rt>>sa (64 BIT MODE)BIT)a)
DSRLV rd,rt,rs: Doubleword SHIFT RIGHT LOGICAL VARIABLE; (64 BIT MODE)BIT)a)
DSRL32 rd,rt,sa: Doubleword SHIFT RIGHT LOGIC+32; rd=rt>>(sa+32) (64 BIT))a)
DSUB rd,rs,rt: Doubleword SUBSTRACT; rd=rs-rt (64 BIT)t>>(sa+32) (64 BIT))a)
DSUBU rd,rs,rt: Doubleword SUBSTRACT UNSIGNED; rd=rs-rt (64 BIT) (64 BIT))a)
ERET : EXCEPTION RETURN: returns from an interrupt, exception or error trap)
J target: JUMP: unconditionally jumps to targetupt, exception or error trap)
JAL target: JUMP AND LINK: call a subroutine at target. (return adr in \$ra))
JALR rd,rs: JUMP AND LINK: call a subroutine at rs. (return adr in rd) \$ra))
JR rs: JUMP REGISTER: unconditionally jumps to the adress contained in rsa))
LB rt,offset(base): LOAD BYTE; rt=byte[base+offset] (SIGNED)ntained in rsa))
LBU rt,offset(base): LOAD BYTE UNSIGNED; rt=byte[base+offset]tained in rsa))
LD rt,offset(base): LOAD DOUBLEWORD; rt=doubleword[base+offset] (64 BIT)sa))
LDCn rt,offset(base): LOAD DOUBLEWORD TO COP n; COP rt=d[base+offset]IT)sa))
LDL rt,offset(base): LOAD DOUBLEWORD LEFT; left(rt)=r[base+offset] (64 BIT))
LDR rt,offset(base): LOAD DOUBLEWORD RIGHT; right(rt)=l[base+offset] (64 BIT)
LH rt,offset(base): LOAD HALFWORD; rt=halfword[base+offset] (SIGNED) (64 BIT)
LHU rt,offset(base): LOAD HALFWORD UNSIGNED; rt=halfword[base+offset](64 BIT)
LL rt,offset(base): LOAD LINKEDORD UNSIGNED; rt=halfword[base+offset](64 BIT)
LLD rt,offset(base): LOAD LINKED DOUBLEWORD; (64 BIT MODE)ase+offset](64 BIT)
LUI rt,imm: LOAD UPPER IMMEDIATE; rt=imm*10000h4 BIT MODE)ase+offset](64 BIT)
LW rt,offset(base): LOAD WORD; rt=word[base+offset]T MODE)ase+offset](64 BIT)
LWCn rt,offset(base): LOAD WORD TO COPROCESSOR n; COP rt=word[base+offset]IT)
LWL rt,offset(base): LOAD WORD LEFT; left(rt)=right[base+offset]se+offset]IT)
LWR rt,offset(base): LOAD WORD RIGHT; right(rt)=left[base+offset]e+offset]IT)
LWU rt,offset(base): LOAD WORD UNSIGNED; rt=word[base+offset]; (64 BIT MODE))
MFCn rt,rd: MOVE FROM SYSTEM CONTROL COPROCESSOR n; rt=COP rd; (64 BIT MODE))
MFHI rd: MOVE FROM HI; rd=HI CONTROL COPROCESSOR n; rt=COP rd; (64 BIT MODE))
MFLO rd: MOVE FROM LO; rd=LO CONTROL COPROCESSOR n; rt=COP rd; (64 BIT MODE))
MTCn rt,rd: MOVE TO SYSTEM CONTROL COPROCESSOR n; COP rd=rtrd; (64 BIT MODE))
MULT rs,rt: MULTIPLY; LO=low(rs*rt); HI=high(rs*rt)OP rd=rtrd; (64 BIT MODE))
MULTU rs,rt: MULTIPLY UNSIGNED; LO=low(rs*rt); HI=high(rs*rt); (64 BIT MODE))
NOP : NO OPERATION; do nothing; LO=low(rs*rt); HI=high(rs*rt); (64 BIT MODE))
NOR rd,rs,rt: logical NOR; rd=(rs NOR rt)*rt); HI=high(rs*rt); (64 BIT MODE))
OR rd,rs,rt: logical OR; rd=(rs OR rt)rt)*rt); HI=high(rs*rt); (64 BIT MODE))
ORI rt,rs,imm: logical OR IMMEDIATE; rd=(rs OR imm)igh(rs*rt); (64 BIT MODE))
SB rt,offset(base): STORE BYTE; byte[base+offset]=rtgh(rs*rt); (64 BIT MODE))
SC rt,offset(base): STORE CONDITIONALbase+offset]=rtgh(rs*rt); (64 BIT MODE))
SCD rt,offset(base): STORE CONDITIONAL DOUBLEWORD (64 BIT MODE)(64 BIT MODE))
SD rt,offset(base): STORE DOUBLEWORD; dword[base+offset]=rt (64 BIT)IT MODE))
SDCn rt,offset(base): STORE DOUBLEWORD FROM COP n; d[base+offset]=COP rtODE))
SDL rt,offset(base): STORE DOUBLEWORD LEFT; r[base+offset]=left(rt) (64 BIT))
SDR rt,offset(base): STORE DOUBLEWORD RIGHT;l[base+offset]=right(rt) (64BIT))
SH rt,offset(base): STORE HALFWORD; halfword[base+offset]=rtight(rt) (64BIT))
SLL rd,rt,sa: SHIFT LEFT LOGICAL; rd=rt<<sad[base+offset]=rtight(rt) (64BIT))
SLLV rd,rt,rs: SHIFT LEFT LOGICAL VARIABLE; rd=rt<<rsset]=rtight(rt) (64BIT))
SLT rd,rs,rt: SET ON LESS THAN; rd=1 if rs<rt (UNSIGNED) else rd=0t) (64BIT))
SLTI rd,rs,imm: SET ON LESS THAN IMMEDIATE; rd=1 if rs<imm (SIGND) else rd=0)
SLTIU rd,rs,imm: SET ON LESS THAN IMM UNSIGNED; rd=1 if rs<imm else rd=0rd=0)
SLTU rd,rs,rt: SET ON LESS THAN UNSIGNED; rd=1 if rs<rt else rd=0se rd=0rd=0)
SRA rd,rt,sa: SHIFT RIGHT ARITHMETIC; rd=rt>>saif rs<rt else rd=0se rd=0rd=0)
SRAV rd,rt,rs: SHIFT RIGHT ARITHMETIC VARIABLE rd=rt<<rslse rd=0se rd=0rd=0)
SRL rd,rt,sa: SHIFT RIGHT LOGICAL; rd=rt>>saLE rd=rt<<rslse rd=0se rd=0rd=0)
SRLV rd,rt,rs: SHIFT RIGHT LOGICAL VARIABLE; rd=rt>>rs<rslse rd=0se rd=0rd=0)
SUB rd,rs,rt: SUBSTRACT; rd=rs-rt; traps if overflowss<rslse rd=0se rd=0rd=0)
SUBU rd,rs,rt: SUBSTRACT UNSIGNED; rd=rs-rt; no trap on overflow0se rd=0rd=0)
SW rt,offset(base): STORE WORD; word[base+offset]=rt on overflow0se rd=0rd=0)
SWCn rt,offset(base): STORE WORD FROM COP n; word[base+offset]=COP rtd=0rd=0)
SWL rt,offset(base): STORE WORD LEFT; right[base+offset]=left(rt)P rtd=0rd=0)
SWR rt,offset(base): STORE WORD RIGHT; left[base+offset]=right(rt) rtd=0rd=0)
SYNC : SYNCHRONIZE): STORE WORD RIGHT; left[base+offset]=right(rt) rtd=0rd=0)
SYSCALL : SYSTEM CALL; system call exception occursfset]=right(rt) rtd=0rd=0)
TEQ rs,rt: TRAP IF EQUAL; if rs=rt then a trap exception occursrt) rtd=0rd=0)
TEQI rs,imm: TRAP IF EQUAL IMMEDIATE; if rs=imm then a trap exception occurs)
TGE rs,rt: TRAP IF GREATER THAN OR EQUAL; if rs>=rt then trapxception occurs)
TGEI rs,imm: TRAP IF GREATER THAN OR EQUAL IMMEDIATE; if rs>=imm then traprs)
TGEIU rs,imm: TRAP IF GREATER THAN OR EQUAL IMM UNSIGNED; if rs>=imm traprs)
TGEU rs,rt: TRAP IF GREATER THAN OR EQUAL UNSIGNED; if rs>=rt then trapraprs)
TLBP : PROBE TLB FOR MATCHING ENTRY EQUAL UNSIGNED; if rs>=rt then trapraprs)
TLBR : READ INDEXED TLB ENTRY ENTRY EQUAL UNSIGNED; if rs>=rt then trapraprs)
TLBWI : WRITE INDEXED TLB ENTRYNTRY EQUAL UNSIGNED; if rs>=rt then trapraprs)
TLBWR : WRITE RANDOM TLB ENTRYYNTRY EQUAL UNSIGNED; if rs>=rt then trapraprs)
TLT rs,rt: TRAP IF LESS THAN; if rs<rt then trapED; if rs>=rt then trapraprs)
TLTI rs,imm: TRAP IF LESS THAN IMMEDIATE; if rs<imm then trap (SIGNED)praprs)
TLTIU rs,imm: TRAP IF LESS THAN IMMEDIATE UNSIGNED; if rs<imm then trapraprs)
TLTU rs,rt: TRAP IF LESS THAN UNSIGNED; if rs<rt then trapimm then trapraprs)
TNE rs,rt: TRAP IF NOT EQUAL; if rs<>rt then trapthen trapimm then trapraprs)
TNEI rs,imm: TRAP IF NOT EQUAL IMMEDIATE; if rs<>imm then trapthen trapraprs)
XOR rd,rs,rt: logical XOR; rd=(rs XOR rt) if rs<>imm then trapthen trapraprs)
XORI rt,rs,imm: logical XOR IMMEDIATE; rd=(rs XOR imm)hen trapthen trapraprs)

Yes, it probably seems like Jibberish and hyroglyphics to you, but all you really need to see right now is the capped letters on the far left - those are the commands. The next set of capped text is the more exact and detailed definition of what the commands do.
Once you learn a little bit more about this, the other crap will become important. But for now, forget it.

Source

[Arnachy69]

Has anybody the good Tools for using Pyiiasmh
like Qt Pyhton and these things

Thx in advance

[XaN]

Has anybody the good Tools for using Pyiiasmh
like Qt Pyhton and these things

Thx in advance

Qt python and the other "tools" you are asking for are dependencies for the program to run, they are all publicly available.

https://www.python.org/downloads/

http://www.qt.io/download/

https://riverbankcomputing.com/software/pyqt/download5

https://code.google.com/archive/p/pyiiasmh/downloads

[Arnachy69]

qt i can not download best man
i was search for the SDK Nokia Release of it but is out
with ohter words de server of it is down

[XaN]

qt i can not download best man
i was search for the SDK Nokia Release of it but is out
with ohter words de server of it is down

Then wait until their server is back up. You would never want to get a SDK from individuals when it's publicly available from the source.

[Arnachy69]

haha okay Xan but i gues the server is temporly down forever and not for a maintenance i'll think
when i search for the Nokia site and than
Nokia SDK QT the site is unavaileble to

[XaN]

haha okay Xan but i gues the server is temporly down forever and not for a maintenance i'll think
when i search for the Nokia site and than
Nokia SDK QT the site is unavaileble to

Wow That would be surprising to me Nokia is a big company, but if they did drop their SDK from the public than you would have to find someone that has it. good luck with your search

[Arnachy69]

it works now Xan but can you learn me how to make an gecko wiird code to an ASM code?
this is 99 lives for Donkey Kong Country Virtual Console game

Have 99 Lives
008AE99D 00000063

how i can convert this code to an ASM code?